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FEATURES 4 mA-20 mA, 0 mA-20 mA or 0 mA-24 mA Current Output 16-Bit Resolution and Monotonicity 0.012% Max Integral Nonlinearity 0.05% Max Offset (Trimmable) 0.15% Max Total Output Error (Trimmable) Flexible Serial Digital Interface (3.3 MBPS) On-Chip Loop Fault Detection On-Chip 5 V Reference (25 ppm/ C Max) Asynchronous CLEAR Function Maximum Power Supply Range of 32 V Output Loop Compliance of 0 V to VCC - 2.5 V 24-Lead SOIC and PDIP Packages PRODUCT DESCRIPTION
Serial Input 16-Bit 4 mA-20 mA, 0 mA-20 mA DAC AD420
FUNCTIONAL BLOCK DIAGRAM
VCC VLL REF OUT REFERENCE 4k 40 BOOST
AD420
REF IN DATA OUT CLEAR LATCH CLOCK DATA IN RANGE SELECT 1 RANGE SELECT 2 CLOCK DATA I/P REGISTER
IOUT 16-BIT DAC SWITCHED CURRENT SOURCES AND FILTERING VOUT 1.25k FAULT DETECT
The AD420 is a complete digital to current loop output converter, designed to meet the needs of the industrial control market. It provides a high precision, fully integrated, low cost single-chip solution for generating current loop signals in a compact 24-lead SOIC or PDIP package. The output current range can be programmed to 4 mA-20 mA, 0 mA-20 mA or an overrange function of 0 mA-24 mA. The AD420 can alternatively provide a voltage output from a separate pin that can be configured to provide 0 V-5 V, 0 V-10 V, 5 V or 10 V with the addition of a single external buffer amplifier. The 3.3M Baud serial input logic design minimizes the cost of galvanic isolation and allows for simple connection to commonly used microprocessors. It can be used in three-wire or asynchronous mode and a serial-out pin is provided to allow daisy chaining of multiple DACs on the current loop side of the isolation barrier. The AD420 uses sigma-delta () DAC technology to achieve 16-bit monotonicity at very low cost. Full-scale settling to 0.1% occurs within 3 ms. The only external components that are required (in addition to normal transient protection circuitry) are two low cost capacitors which are used in the DAC output filter. If the AD420 is going to be used at extreme temperatures and supply voltages, an external output transistor can be used to minimize power dissipation on the chip via the "BOOST" pin. The FAULT DETECT pin signals when an open circuit occurs in the loop. The on-chip voltage reference can be used to supply a precision +5 V to external components in addition to the AD420 or, if the user desires temperature stability exceeding 25 ppm/C, an external precision reference such as the AD586 can be used as the reference.
SPI is a registered trademark of Motorola. MICROWIRE is a registered trademark of National Semiconductor.
OFFSET CAP 1 TRIM
CAP 2
GND
The AD420 is available in a 24-lead SOIC and PDIP over the industrial temperature range of -40C to +85C.
PRODUCT HIGHLIGHTS
1. The AD420 is a single chip solution for generating 4 mA- 20 mA or 0 mA-20 mA signals at the "controller end" of the current loop. 2. The AD420 is specified with a power supply range from 12 V to 32 V. Output loop compliance is 0 V to VCC - 2.5 V. 3. The flexible serial input can be used in three-wire mode with SPI(R) or MICROWIRE(R) microcontrollers, or in asynchronous mode which minimizes the number of control signals required. 4. The serial data out pin can be used to daisy chain any number of AD420s together in three-wire mode. 5. At power-up the AD420 initializes its output to the low end of the selected range. 6. The AD420 has an asynchronous CLEAR pin which sends the output to the low end of the selected range (0 mA, 4 mA, or 0 V). 7. The AD420 BOOST pin accommodates an external transistor to off-load power dissipation from the chip. 8. The offset of 0.05% and total output error of 0.15% can be trimmed if desired, using two external potentiometers.
REV. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
AD420-SPECIFICATIONS (T = T
A
MIN -TMAX,
VCC = +24 V, unless otherwise noted)
AX-32 Version1 Typ Max Units Bits RL = 500 20 20 24 VCC - 2.5 V 3 mA mA mA V ms M Bits % % ppm/C % ppm/C A/V V Comments
Parameter RESOLUTION IOUT CHARACTERISTICS Operating Current Ranges
Min 16 4 0 0 0
Current Loop Voltage Compliance Settling Time (to 0.1% of FS)2 Output Impedance (Current Mode) Accuracy 3 Monotonicity Integral Nonlinearity Offset (0 mA or 4 mA) (TA = +25C) Offset Drift Total Output Error (20 mA or 24 mA) (TA = +25C) Total Output Error Drift PSRR4 VOUT CHARACTERISTICS FS Output Voltage Range (Pin 17) VOLTAGE REFERENCE REF OUT Output Voltage (T A = +25C) Drift Externally Available Current Short Circuit Current REF IN Resistance VLL Output Voltage Externally Available Current Short Circuit Current DIGITAL INPUTS VIH (Logic 1) VIL (Logic 0) IIH (V IN = 5.0 V) IIL (V IN = 0 V) Data Input Rate ("3-Wire" Mode) Data Input Rate ("Asynchronous" Mode) DIGITAL OUTPUTS FAULT DEFECT VOH (10 k Pull-Up Resistor to V LL) VOL (10 k Pull-Up Resistor to V LL) VOL @ 2.5 mA DATA OUT VOH (IOH = -0.8 mA) VOL (IOL = 1.6 mA) POWER SUPPLY Operating Range V CC Quiescent Current Quiescent Current (External VLL ) TEMPERATURE RANGE Specified Performance
NOTES
1 2
2.5 25 16 0.002 20 20 5 0
0.012 0.05 50 0.15 50 10 5
4.995
5.0 5 7 30 4.5 5 20
5.005 25
V ppm/C mA mA k V mA mA V V A A MBPS kBPS
2.4 0.8 10 10 3.3 150
No Minimum No Minimum
3.6
4.5 0.2 0.6 4.3 0.3
0.4
V V V V V V mA mA C
3.6
0.4 32 5.5
12 4.2 3 -40
+85
X refers to package designator, R or N. External capacitor selection must be as described in Figure 5. 3 Total Output Error includes Offset and Gain Error. Total Output Error and Offset Error are with respect to the Full-Scale Output and are measured with an ideal +5 V reference. If the internal reference is used, the reference errors must be added to the Offset and Total Output Errors. 4 PSRR is measured by varying VCC from 12 V to its maximum 32 V. Specifications subject to change without notice.
-2-
REV. F
AD420
ABSOLUTE MAXIMUM RATINGS*
VCC
23
VCC to GND AD420AR/AN-32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 V IOUT to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC Digital Inputs to GND . . . . . . . . . . . . . . . . . . . -0.5 V to +7 V Digital Output to GND . . . . . . . . . . . . . -0.5 V to VLL + 0.3 V VLL and REF OUT: Outputs Safe for Indefinite Short to Ground Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300C Thermal Impedance: SOIC (R) Package . . . . . . . . . . . . . . . . . . . . . . JA = 75C/W PDIP (N) Package . . . . . . . . . . . . . . . . . . . . . . JA = 50C/W
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
VLL 2 REF OUT 14
REFERENCE 4k 40
19
AD420
REF IN 15 DATA OUT 10 CLEAR 6 LATCH 7 CLOCK 8 DATA IN
9
BOOST
CLOCK
18
IOUT VOUT
DATA I/P REGISTER
16-BIT DAC
17
RANGE 5 SELECT 1 RANGE 4 SELECT 2
16
SWITCHED CURRENT SOURCES AND FILTERING
1.25k
3
FAULT DETECT
20
21
11
OFFSET CAP 1 CAP 2 GND TRIM
Figure 1. Functional Block Diagram
Table I. Truth Table
ORDERING GUIDE
Model
Temperature Range
Max Operating Package Voltage Options* 32 V 32 V N-24 R-24 CLEAR 0 1 X X X X
Inputs Range Select 2 X X 0 0 1 1 Range Select 1 X X 0 1 0 1 Operation Normal Operation Output at Bottom of Span 0 V-5 V Range 4 mA-20 mA Range 0 mA-20 mA Range 0 mA-24 mA Range
AD420AN-32 - 40C to +85C AD420AR-32 - 40C to +85C
*N = Plastic DIP, R = Plastic SOIC.
PIN DESIGNATIONS
NC VL L FAULT DETECT RANGE SELECT 2 RANGE SELECT 1 CLEAR LATCH CLOCK DATA IN DATA OUT GND NC NC = NO CONNECT NC VCC NC CAP2
AD420
TOP VIEW (Not to Scale)
CAP1 BOOST IOUT VOUT OFFSET TRIM REF IN REF OUT NC
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD420 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. F
-3-
AD420 Timing Requirements (T = -40 C to +85 C, V
A CC
= +12 V to +32 V)
THREE-WIRE INTERFACE
CLOCK CLOCK WORD "N" DATA IN 10 (MSB) B15 B14 11 B13 B12 00 B11 B10 1 B9 00 B8 B7 111 B6 B5 B4 00 B3 B2 11 B1 B0 (LSB) WORD "N + 1" 1 B15 00 1 B14 B13 B12 DATA IN 0 START BIT 1 BIT 15 0 BIT 14 BITs 13-1 0 BIT 0 1 STOP BIT NEXT START BIT
(INTERNALLY GENERATED LATCH)
LATCH EXPANDED TIME VIEW BELOW WORD "N - 1" DATA OUT WORD "N" 10 B15 B14 11 B13 B12 CLOCK 01 DATA IN 2 8 START BIT 16 24 DATA BIT 15 BIT 14 CLOCK COUNTER STARTS HERE CONFIRM START BIT SAMPLE BIT 15
tCK tCL
CLOCK
tCH tDS tDH
DATA IN
EXPANDED TIME VIEW BELOW
tDW tLD
LATCH
tACK tACL tLL tLH tSD
CLOCK
tADS tADW
DATA IN
tACH tADH
DATA OUT
Figure 2. Timing Diagram for Three-Wire Interface
Table II. Timing Specification for Three-Wire Interface
Figure 3. Timing Diagram for Asynchronous Interface
Table III. Timing Specifications for Asynchronous Interface
Parameter Data Clock Period Data Clock Low Time Data Clock High Time Data Stable Width Data Setup Time Data Hold Time Latch Delay Time Latch Low Time Latch High Time Serial Output Delay Time Clear Pulsewidth
Label tCK tCL tCH tDW tDS tDH tLD tLL tLH tSD tCLR
Limit 300 80 80 125 40 5 80 80 80 225 50
Units ns min ns min ns min ns min ns min ns min ns min ns min ns min ns max ns min
Parameter Asynchronous Clock Period Asynchronous Clock Low Time Asynchronous Clock High Time Data Stable Width (Critical Clock Edge) Data Setup Time (Critical Clock Edge) Data Hold Time (Critical Clock Edge) Clear Pulsewidth
ASYNCHRONOUS INTERFACE
Label Limit Units tACK tACL tACH tADW tADS tADH tCLR 400 50 150 300 50 20 50 ns min ns min ns min ns min ns min ns min ns min
Three-Wire Interface Fast Edges on Digital Input
With a fast rising edge (<10 ns) on one of the serial inputs (CLOCK, DATA IN, LATCH) while another input is logic high, the part may be triggered into a test mode and the contents of the data register may become corrupted, which may result in the output being loaded with an incorrect value. If fast edges are expected on the digital input lines, it is recommended that the latch line remain at Logic 0 during serial loading of the DAC. Similarly, the clock line should remain low during updates of the DAC via the latch pin. Alternatively, the addition of small value capacitors on the digital lines will slow down the edge.
Note in the timing diagram for asynchronous mode operation each data word is "framed" by a START (0) bit and a STOP (1) bit. The data timing is with respect to the rising edge of the CLOCK at the center of each bit cell. Bit cells are 16 clocks long, and the first cell (the START bit) begins at the first clock following the leading (falling) edge of the START bit. Thus the MSB (D15) is sampled 24 clock cycles after the beginning of the START bit, D14 is sampled at clock number 40, and so on. During any "dead time" before writing the next word the DATA IN pin must remain at Logic 1. The DAC output updates when the STOP bit is received. In the case of a "framing error" (the STOP bit sampled as a 0) the AD420 will output a pulse at the DATA OUT pin one clock period wide during the clock period subsequent to sampling the STOP bit. The DAC output will not update if a "framing error" is detected.
-4-
REV. F
AD420
PIN DESCRIPTION
Pin # 1, 12, 13, 24 2
Symbol NC VLL
Function No Connection. No internal connections inside device. Auxiliary buffered +4.5 V digital logic voltage. This pin is the internal supply voltage for the digital circuitry and can be used as a termination for pull-up resistors. An external +5 V power supply can be connected to VLL. It will override this buffered voltage, thus reducing the internal power dissipation. The VLL pin should be decoupled to GND with a 0.1 F capacitor. See Power Supplies and Decoupling section. FAULT DETECT, connected to a pull-up resistor, is asserted low when the output current does not match the DAC's programmed value, for example, in case the current loop is broken. Selects the converter's output operating range. One output voltage range and three output current ranges are available. Valid VIH will unconditionally force the output to go to the minimum of its programmed range. After CLEAR is removed the DAC output will remain at this value. The data in the input register is unaffected. In the three-wire interface mode a rising edge parallel loads the serial input register data into the DAC. To use the asynchronous mode connect LATCH through a current limiting resistor to VCC. Data Clock Input. The clock period is equal to the input data bit rate in the threewire interface mode and is 16 times the bit rate in asynchronous mode. Serial Data Input. Serial Data Output. In the three-wire interface mode, this output can be used for daisy-chaining multiple AD420s. In the asynchronous mode a positive pulse will indicate a framing error after the stop-bit is received. Ground (Common). +5 V Reference Output. Reference Input. Offset Adjust. Voltage Output. Current Output. Connect to an external transistor to reduce the power dissipated in the AD420 output transistor, if desired. These pins are used for internal filtering. Connect capacitors between each of these pins and VCC. Refer to the description of current output operation. No Connection. Do not connect anything to this pin. Power Supply Input. The VCC pin should always be decoupled to GND with a 0.1 F capacitor. See Power Supplies and Decoupling section. GAIN ERROR: Gain error is a measure of the output error between an ideal DAC and the actual device output with all 1s loaded after offset error has been adjusted out. OFFSET ERROR: Offset error is the deviation of the output current from its ideal value expressed as a percentage of the fullscale output with all 0s loaded in the DAC. DRIFT: Drift is the change in a parameter (such as gain and offset) over a specified temperature range. The drift temperature coefficient, specified in ppm/C, is calculated by measuring the parameter at TMIN, 25C, and T MAX and dividing the change in the parameter by the corresponding temperature change. CURRENT LOOP VOLTAGE COMPLIANCE: The voltage compliance is the maximum voltage at the IOUT pin for which the output current will be equal to the programmed value.
3
FAULT DETECT
4 5 6
RANGE SELECT 2 RANGE SELECT 1 CLEAR
7
LATCH
8 9 10
CLOCK DATA IN DATA OUT
11 14 15 16 17 18 19 20 21 22 23
GND REF OUT REF IN OFFSET TRIM VOUT IOUT BOOST CAP 1 CAP 2 NC VCC
DEFINITIONS OF SPECIFICATIONS
RESOLUTION: For 16-bit resolution, 1 LSB = 0.0015% of the FSR. In the 4 mA-20 mA range 1 LSB = 244 nA. INTEGRAL NONLINEARITY: Analog Devices defines integral nonlinearity as the maximum deviation of the actual, adjusted DAC output from the ideal analog output (a straight line drawn from 0 to FS - 1 LSB) for any bit combination. This is also referred to as relative accuracy. DIFFERENTIAL NONLINEARITY: Differential nonlinearity is the measure of the change in the analog output, normalized to full scale, associated with an LSB change in the digital input code. Monotonic behavior requires that the differential linearity error be greater than -1 LSB over the temperature range of interest. MONOTONICITY: A DAC is monotonic if the output either increases or remains constant for increasing digital inputs with the result that the output will always be a single-valued function of the input.
REV. F
-5-
AD420
THEORY OF OPERATION
The AD420 uses a sigma-delta () architecture to carry out the digital-to-analog conversion. This architecture is particularly well suited for the relatively low bandwidth requirements of the industrial control environment because of its inherent monotonicity at high resolution. In the AD420 a second order modulator is used to keep complexity and die size to a minimum. The single bit stream from the modulator controls a switched current source that is then filtered by two, continuous time resistor-capacitor sections. The capacitors are the only external components that have to be added for standard current-out operation. The filtered current is amplified and mirrored to the supply rail so that the application simply sees a 4 mA-20 mA, 0 mA-20 mA, or 0 mA-24 mA current source output with respect to ground. The AD420 is manufactured on a BiCMOS process that is well suited to implementing low voltage digital logic with high performance and high voltage analog circuitry. The AD420 can also provide a voltage output instead of a current loop output if desired. The addition of a single external amplifier allows the user to obtain 0 V-5 V, 0 V-10 V, 5 V, or 10 V. The AD420 has a loop fault detection circuit that warns if the voltage at IOUT attempts to rise above the compliance range, due to an open-loop circuit or insufficient power supply voltage. The FAULT DETECT is an active low open drain signal so that one can connect several AD420s together to one pull-up resistor for global error detection. The pull-up resistor can be tied to the VLL pin, or an external +5 V logic supply. The I OUT current is controlled by a PMOS transistor and internal amplifier as shown in the functional block diagram. The internal circuitry that develops the fault output avoids using a comparator with "window limits" since this would require an actual output error before the FAULT DETECT output becomes active. Instead, the signal is generated when the internal amplifier in the output stage of the AD420 has less than approximately
one volt remaining of drive capability (when the gate of the output PMOS transistor nearly reaches ground). Thus the FAULT DETECT output activates slightly before the compliance limit is reached. Since the comparison is made within the feedback loop of the output amplifier, the output accuracy is maintained by its open-loop gain, and no output error occurs before the fault detect output becomes active. The three-wire digital interface, comprising DATA IN, CLOCK, and LATCH, interfaces to all commonly used serial microprocessors without the addition of any external glue logic. Data is loaded into an input register under control of CLOCK and is loaded to the DAC when LATCH is strobed. If a user wants to minimize the number of galvanic isolators in an intrinsically safe application, the AD420 can be configured to run in "asynchronous" mode. This mode is selected by connecting the LATCH pin to VCC through a current limiting resistor. The data must then be combined with a start and stop bit to "frame" the information and trigger the internal LATCH signal.
VCC
23
VLL 2 REF OUT 14
REFERENCE 4k 40
19
AD420
REF IN 15 DATA OUT 10 CLEAR 6 LATCH 7 CLOCK 8 DATA IN 9 RANGE 5 SELECT 1 RANGE 4 SELECT 2
16
BOOST
CLOCK
18
IOUT VOUT
DATA I/P REGISTER
16-BIT DAC
17
SWITCHED CURRENT SOURCES AND FILTERING
1.25k
3
FAULT DETECT
20
21
11
OFFSET CAP 1 CAP 2 GND TRIM
Figure 4. Functional Block Diagram
-6-
REV. F
AD420
APPLICATIONS
CURRENT OUTPUT Table IV. Buffer Amplifier Configuration
The AD420 can provide 4 mA-20 mA, 0 mA-20 mA, or 0 mA- 24 mA output without any active external components. Filter capacitors C1 and C2 can be any type of low cost ceramic capacitors. To meet the specified full-scale settling time of 3 ms, low dielectric absorption capacitors (NPO) are required. Suitable values are C1 = 0.01 F and C2 = 0.01 F.
0.1 F VCC VLL C1 2 RANGE SELECT 1 RANGE SELECT 2 CLEAR LATCH CLOCK DATA IN 5 4 6 7 8 9 REF OUT 14 15 REF IN 11 GND IOUT (4mA-20mA) 20 C2 21 23 0.1 F
R1 Open Open R R
R2 Open R Open 2R
R3 0 R R 2R
VOUT 0 V-5 V 0 V-10 V 5 V 10 V
Suitable R = 5 k.
OPTIONAL SPAN AND ZERO TRIM
For those users who would like lower than specified values of offset and gain error, Figure 7 shows a simple way to trim these parameters. Care should be taken to select low drift resistors because they will affect the temperature drift performance of the DAC. The adjustment algorithm is iterative. The procedure for trimming the AD420 in the 4 mA-20 mA mode can be accomplished as follows: STEP I . . . OFFSET ADJUST Load all zeros. Adjust RZERO for 4.00000 mA of output current. STEP II . . . GAIN ADJUST Load all ones. Adjust RSPAN for 19.99976 mA (FS - 1 LSB) of output current. Return to STEP I and iterate until convergence is obtained.
VCC VLL 0.1 F RANGE SELECT1 RANGE SELECT2 CLEAR LATCH 2 5 4 6 7 8 9 14 VREF 500 RSPAN 10k RZERO GND 15 16 11 19 C1 20 C2 21 23 0.1 F 5k RSPAN2 BOOST IOUT (4mA-20mA) 18 RLOAD
AD420
18 RLOAD
Figure 5. Standard Configuration
DRIVING INDUCTIVE LOADS
When driving inductive or poorly defined loads connect a 0.01 F capacitor between IOUT (Pin 18) and GND (Pin 11). This will ensure stability of the AD420 with loads beyond 50 mH. There is no maximum capacitance limit. The capacitive component of the load may cause slower settling, though this may be masked by the settling time of the AD420. A programmed change in the current may cause a back EMF voltage on the output that may exceed the compliance of the AD420. To prevent this voltage from exceeding the supply rails connect protective diodes between IOUT and each of VCC and GND.
VOLTAGE-MODE OUTPUT
AD420
CLOCK DATA IN
Since the AD420 is a single supply device, it is necessary to add an external buffer amplifier to the VOUT pin to obtain a selection of bipolar output voltage ranges as shown in Figure 6.
VCC VLL 0.1 F 2 RANGE SELECT 1 RANGE SELECT 2 CLEAR LATCH CLOCK DATA IN 5 4 6 7 8 9 REF OUT 14 15 REF IN 11 GND R1 VOUT 17 VOUT 20 C1 21 C2 23 0.1 F
Figure 7. Offset and Gain Adjust
AD420
Variation of RZERO between REF OUT (5 V) and GND leads to an offset adjust range from -1.5 mA to 6 mA, (1.5 mA/V centered at 1 V). The 5 k RSPAN2 resistor is connected in parallel with the internal 40 sense resistor, which leads to a gain increase of +0.8%. As RSPAN is changed to 500 , the voltage on REF IN is attenuated by the combination of RSPAN and the 30 k REF IN input resistance. When added together with RSPAN2 this results in an adjustment range of -0.8% to +0.8%.
R3 R2
Figure 6.
REV. F
-7-
AD420
THREE-WIRE INTERFACE ASYNCHRONOUS INTERFACE USING OPTOCOUPLERS
Figure 8 shows the AD420 connected in the three-wire interface mode. The AD420 data input block contains a serial input shift register and a parallel latch. The contents of the shift register are controlled by the DATA IN signal and the rising edges of the CLOCK. Upon request of the LATCH pin the DAC and internal latch are updated from the shift register parallel outputs. The CLOCK should remain inactive while the DAC is updated. Refer to the timing requirements for three-wire interface.
FAULT DETECT VCC VLL FAULT DETECT LATCH CLOCK DATA IN LATCH CLOCK DATA IN GND VCC 10k FAULT DETECT VCC VCC
AD420
DAC1
DATA OUT IOUT RLOAD
LATCH CLOCK DATA IN GND
AD420
DAC2
DATA OUT IOUT RLOAD
The AD420 connected in ASYNCHRONOUS INTERFACE mode with optocouplers is shown in Figure 9. Asynchronous operation minimizes the number of control signals required for isolation of the digital system from the control loop. The resistor connected between the LATCH pin and VCC is required to activate this mode. For operation with VCC below 18 V use a 50 k pull-up resistor, from 18 V-32 V use 100 k. Asynchronous mode requires that the clock run at 16 times the data bit rate, therefore to operate at the maximum input data rate of 150 kBPS an input clock of 2.4 MHz is required. The actual data rate achieved may be limited by the type of optocouplers chosen. The number of control signals can further be reduced by creating the appropriate clock signal on the current loop side of the isolation barrier. If optocouplers with relatively slow rise and fall times are used, Schmitt triggers may be required on the digital inputs to prevent erroneous data being presented to the DAC.
+24V 23 VCC 100k 7 LATCH
Figure 8. Three-Wire Interface Using Multiple DACs with Joint Fault Detect
USING MULTIPLE DACS WITH FAULT DETECT
CLOCK
+5V
2 8
VLL CLOCK
The three-wire interface mode can utilize the serial DATA OUT for easy interface to multiple DACs. To program the two AD420s in Figure 8, 32 data bits are required. The first 16 bits are clocked into the input shift register of DAC1. The next 16 bits transmitted pass the first 16 bits from the DATA OUT pin of DAC1 to the input register of DAC2. The input shift registers of the two DACs operate as a single 32-bit shift register, with the leading 16 bits representing information for DAC2 and the trailing 16 bits serving for DAC1. Each DAC is then updated upon request of the LATCH pin. The daisy-chain can be extended to as many DACs as required.
AD420
9 DATA IN
DATA
11 GND GALVANIC ISOLATION BARRIER
Figure 9. Asynchronous Interface Using Optocouplers
-8-
REV. F
AD420
MICROPROCESSOR INTERFACE SECTION
AD420-TO-MC68HC11 (SPI BUS) INTERFACE
SO DATA IN CLOCK LATCH
The AD420 interface to the Motorola SPI (Serial Peripheral Interface) is shown in Figure 10. The MOSI, SCK, and SS pins of the HC11 are respectively connected to the DATA IN, CLOCK, and LATCH pins of the AD420. The majority of the interfacing issues are done in the software initialization. A typical routine such as the one shown below begins by initializing the state of the various SPI data and control registers.
LDAA STAA LDAA STAA LDAA STAA NEXTPT LDAA BSR JMP SENDAT LDY BCLR STAA WAIT1 LDAA BPL LDAA STAA WAIT2 LDAA BPL BSET RTS INIT #$2F PORTD #$38 DDRD #$50 SPCR MSBY SENDAT NEXTPT #$1000 $08,Y,$20 SPDR SPSR WAIT1 LSBY SPDR SPSR WAIT2; $08,Y,$20 ;SS = 1; SCK = 0; MOSI = 1 ;SEND TO SPI OUTPUTS ;SS, SCK, MOSI = OUTPUTS ;SEND DATA DIRECTION INFO ;DABL INTRPTS, SPI IS MASTER & ON ;CPOL = 0, CPHA = 0, 1MHZ BAUDRATE ;LOAD ACCUM W/UPPER 8 BITS ;JUMP TO DAC OUTPUT ROUTINE ;INFINITE LOOP ;POINT AT ON-CHIP REGISTERS ;DRIVE SS (LATCH) LOW ;SEND MS-BYTE TO SPI DATA REG ;CHECK STATUS OF SPIE ;POLL FOR END OF X-MISSION ;GET LOW 8 BITS FROM MEMORY ;SEND LS-BYTE TO SPI DATA REG ;CHECK STATUS OF SPIE ;POLL FOR END OF X-MISSION ;DRIVE SS HIGH TO LATCH DATA
MICROWIRE
SK G1
AD420
Figure 11. AD420-to-MICROWIRE Interface
EXTERNAL BOOST FUNCTION
The external boost transistor reduces the power dissipated in the AD420 by reducing the current flowing in the on-chip output transistor (dividing it by the current gain of the external circuit). A discrete NPN transistor with a breakdown voltage, BVCEO, greater than 32 V can be used as shown in Figure 12.
MJD31C OR 2N3053
BOOST 19
AD420
IOUT 18
1k 0.022 F
RLOAD
Figure 12. External Boost Configuration
The SPI data port is configured to process data in 8-bit bytes. The most significant data byte (MSBY) is retrieved from memory and processed by the SENDAT routine. The SS pin is driven low by indexing into the PORTD data register and clear Bit 5. The MSBY is then sent to the SPI data register where it is automatically transferred to the AD420 internal shift resister. The HC11 generates the requisite eight clock pulses with data valid on the rising edges. After the MSBY is transmitted, the least significant byte (LSBY) is loaded from memory and transmitted in a similar fashion. To complete the transfer, the LATCH pin is driven high when loading the complete 16-bit word into the AD420.
MOSI DATA IN CLOCK LATCH
The external boost capability has been developed for those users who may wish to use the AD420, in the SOIC package, at the extremes of the supply voltage, load current, and temperature range. The PDIP package (because of its lower thermal resistance) will operate safely over the entire specified voltage, temperature, and load current ranges without the boost transistor. The plot in Figure 13 shows the safe operating region for both package types. The boost transistor can also be used to reduce the amount of temperature induced drift in the part. This will minimize the temperature induced drift of the on-chip voltage reference, which improves drift and linearity.
VCC WHEN USING SOIC PACKAGED DEVICES, AN EXTERNAL BOOST TRANSISTOR IS REQUIRED FOR OPERATION IN THIS AREA
32V 28V
68HC11
SCK SS
AD420
20V
25V
Figure 10. AD420-to-68HC11 (SPI) Interface
12V
AD420 OR AD420-32
AD420-TO-MICROWIRE INTERFACE
The flexible serial interface of the AD420 is also compatible with the National Semiconductor MICROWIRE interface. The MICROWIRE interface is used in microcontrollers such as the COP400 and COP800 series of processors. A generic interface to use the MICROWIRE interface is shown in Figure 11. The G1, SK, and SO pins of the MICROWIRE interface are respectively connected to the LATCH, CLOCK, and DATA IN pins of the AD420.
4V -60 -40 -20 0 20 40 60 80 100
TEMPERATURE - C
Figure 13. Safe Operating Region
REV. F
-9-
AD420
AD420 PROTECTION
TRANSIENT VOLTAGE PROTECTION BOARD LAYOUT AND GROUNDING
The AD420 contains ESD protection diodes which prevent damage from normal handling. The industrial control environment can, however, subject I/O circuits to much higher transients. In order to protect the AD420 from excessively high voltage transients such as those specified in IEC 801, external power diodes and a surge current limiting resistor may be required, as shown in Figure 14. The constraint on the resistor is that during normal operation the output voltage level at IOUT must remain within its voltage compliance limit (IOUT x (Rp + RLOAD) VCC - 2.5 V) and the two protection diodes and resistor must have appropriate power ratings.
VCC
The AD420 ground pin, designated GND, is the "high quality" ground reference point for the device. Any external loads on the REF OUT and VOUT pins of the AD420 should be returned to this reference point. Analog and digital ground currents should not share a common path. Each signal should have an appropriate analog or digital signal return routed close to it. Using this approach, signal loops enclose a small area, minimizing the inductive coupling of noise. Wide PC tracks, large gauge wire, and ground planes are highly recommended to provide low impedance signal paths.
POWER SUPPLIES AND DECOUPLING
VCC
AD420
IOUT
RP RLOAD
GND
The AD420 supply pins, VCC (Pin 23) and VLL (Pin 2), should be decoupled to GND with 0.1 F capacitors to eliminate high frequency noise that may otherwise get coupled into the analog system. High frequency ceramic capacitors are recommended. The decoupling capacitors should be located in close proximity to the pins and the ground line to have maximum effect. Further reductions in noise, and improvements in performance, may be achieved by using a larger value capacitor on the VLL pin.
Figure 14. Output Transient Voltage Protection
-10-
REV. F
AD420
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Lead Plastic DIP (N-24)
1.275 (32.30) 1.125 (28.60)
24 1 13 12
0.280 (7.11) 0.240 (6.10) 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93)
PIN 1 0.210 (5.33) MAX 0.200 (5.05) 0.022 (0.558) 0.125 (3.18) 0.014 (0.356)
0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN 0.100 (2.54) BSC 0.070 (1.77) SEATING PLANE 0.045 (1.15)
0.015 (0.381) 0.008 (0.204)
24-Lead Small Outline (SOIC) (R-24)
0.6141 (15.60) 0.5985 (15.20)
24 13
1
12
PIN 1
0.1043 (2.65) 0.0926 (2.35)
0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00)
0.0291 (0.74) x 45 0.0098 (0.25)
0.0118 (0.30) 0.0040 (0.10)
0.0500 (1.27) BSC
8 0.0500 (1.27) 0.0192 (0.49) SEATING 0.0125 (0.32) 0 0.0157 (0.40) 0.0138 (0.35) PLANE 0.0091 (0.23)
REV. F
-11-
PRINTED IN U.S.A.
C1870e-0-9/99

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